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Features
* * * * * * * * *
Four Independent Receivers OneTransmitter in A Mode Direct 6800 Microprocessor Interface 8-bit Data Bus ARINC Interface: "1" and "0" Lines, RZ Code Software Label Control in A Mode Parity Control: Odd or No Parity Interrupt Capability in A Mode Test Mode Capability
Description
The EF4442 is a reception interface for 4 ARINC 429 channels. Two models of operation are provided: * When in A mode, the circuit can be considered as a peripheral of an EF 6800 or EF6802 microprocessor and is totally software programmable (for example, for test purposes). When in B mode, the parameters are hardware programmed. Reading the registers which contain messages is only possible (max. scan frequency: 2 MHz).
*
ARINC 429 Multi-channel Buffer Receiver (RTA) (N Channel, Silicon Gate) EF4442
Screening Quality
This product is manufactured in full compliance with either: * * * NFC 96883 class G MIL-STD-883 class B According to Atmel standards
Application Note
Ask for application note: "General application principles EF4442(RTA)"
C Suffix DIL 28 Ceramic Side Brazed package
P Suffix DIP 28 Plastic Package
Rev. 2112A-HIREL-11/02
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Figure 1. Block Diagram
H0 L0 H1 L1 H2 L2 H3 L3 N0 N1 INH
Channel 0
Channel 1
Channel 2
Channel 3
Counter N0, N1 Shift register 32 bits
HR Shift register 32 bits 8 24 HE :n Comparator 8 bits 8 Label 8 8 Control register Status 8 Buffer 24 bits 8 24 8 DEMUX 1 -> 3
32
8 Synchro enable :8 Control
24 MUX 3 -> 1 8 Buffer VSS VCC D0 D1 D2 D3 D4 8 8
8 6
MODE CS RW/INH A0
A1
IRQ/V
D5 D6 D7
Table 1. Pin Description
Name Number VSS RW/INH Description This pin is connected to the negative side of the power supply (ground). This input selects the direction of transfer (write or read) of data between the circuit and the microprocessor when the circuit is programmed in mode A (cf. Pin 28). In B mode, this input is used to disable the channel scanning divide by 4 counter. In A mode, this output has a transmit function. The signal corresponding to the result of ANDing. In A mode, this output has a transmit function. The signal corresponding to the result of ANDing the ARINC transmit clock and the complemented output signal of the transmit shift register (logic "0" clock output) is available on this pin. In B mode, the value of the least significant bit of the address of the scanned channel is available on this pin. In A mode, this output has a transmit function. The signal corresponding to the result of ANDing the ARINC transmit clock and the output signal of the transmit shift register (logic "1" clock available on this pin). In B mode, the value of the least significant bit of the address of the scanned channel is available on this pin. In A mode, this input (active when low) selects the chip for a microprocessor access. In A mode, this input corresponds to the most significant bit of the circuit function address. In B mode, this input corresponds to the least significant bit of the address of the data byte in the message. In A mode, this input corresponds to the most significant bit of the circuit function address. In B mode, this input corresponds to the most significant bit of the address of the data byte in the message. This input (active when low) initializes the circuit by resetting some registers.
N0
N1
CS A0 A1 RESET
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Table 1. Pin Description (Continued)
Name Number O D7 D6 D5 D4 VCC D3 D2 D1 D0 L0 H0 L1 H1 L2 H2 L3 H3 IRQ/V Description This input receives the clock signal from the circuit which corresponds to the phase O2 of the microprocessor clock. This tristate input/output is connected to the eighth line of the data bus. This tristate input/output is connected to the seventh line of the data bus. This tristate input/output is connected to the sixth line of the data bus. This tristate input/output is connected to the fifth line of the data bus. This pin is connected to the positive side of the power supply (+5V). This tristate input/output is connected to the fourth line of the data bus. This tristate input/output is connected to the third line of the data bus. This tristate input/output is connected to the second line of the data bus. This tristate input/output is connected to the first line of the data bus. This input receives the logic "0" clock from the signal shaping/separation subsystem of the first ARINC channel. This input receives the logic "1" clock from the signal shaping/separation subsystem of the first ARINC channel. This input receives the logic "0" clock from the signal shaping/separation subsystem of the second ARINC channel. This input receives the logic "1" clock from the signal shaping/separation subsystem of the second ARINC channel. This input receives the logic "0" clock from the signal shaping/separation subsystem of the third ARINC channel. This input receives the logic "1" clock from the signal shaping/separation subsystem of the third ARINC channel. This input receives the logic "0" clock from the signal shaping/separation subsystem of the fourth ARINC channel. This input receives the logic "1" clock from the signal shaping/separation subsystem of the fourth ARINC channel. In A mode, this pin (active when low) constitutes an open drain output delivering the signal for interrupting the microprocessor. In B mode, this pin is an input used to program the number of high speed channels. This input is used to program the operating mode (A or B) of the circuit and also to enable or disable this parity check.
Mode
Description of Registers
The EF4442 circuit features three types of internal register: * * * Registers concerned with general circuit operation, Registers specific to the transmit channel, Registers specific to each receive channel.
General Registers
Status Register This register is used only when the circuit is programmed in A mode. Its contents inform the microprocessor about the status of the circuit functions. Bits S0 and S4 activate output IRQ when at 1 (except S4 which is maskable - cf. description of control register). Bits S0 and S3 at 1 indicate that the channel with the address which corresponds to the rank of the bit has received a correct message (label recognized and correct parity in the case of a circuit programmed to check the parity of messages). Each bit is reset to 0 on reading the registers of the corresponding channel. In transmit mode, bit S4 of the status register is set to 1 when transmission of the message is terminated. 3
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Bit S4 is reset to 0 when control bit C4 (see below) is a 1. Bits S5 and S6 are not used. Bit S7 is at 1 throughout transmission. Control Register This eight-bit register (C0-C7) monitors operation of the circuit in A mode. In receive mode, bits C0-C3 select the corresponding channels for writing or reading when set to 1 by the microprocessor. Bit C4 at 1 enables programming of the transmit channel (data to send and transmission speed). The setting of bit C4 to 1 resets to 0 the index of the four-byte stack constituting the message to send. Bit C5 at 1 is used to initiate transmission of the message. It is set to 0 when transmission is terminated. Bit C6 at 1 simultaneously with bit C5 at 1 loops back the transmitted data to the input of the receive channel selected by bits C0-C3, for test purposes. It is set to 0 by any control register access. Bit C7 at 1 masks status bit S4 and thus prevents activation of output IRQ.
Transmit Channel Registers (A mode only)
Programmable Divider Register This eight-bit register is programmed by the microprocessor and contains the value n of the division ratio (the least significant bit is always considered to be at 0). The programmable divider generates a clock signal at a frequency equal to clock O divided by n. Transmit Register This 32-bit shift register may be programmed in four phases by the microprocessor. This writing must be effected immediately after the setting to 1 of control bit C4 (cf. description of control register). This resets to zero the index of the 4-byte stack. The transmit register shifts the data present in it to the outputs in accordance with the states of the bits in the control register.
Receive Channel Registers
Synchronization/Enable Register
Each receive channel comprises the following registers:
This eight-bit register is programmable by the microprocessor. The most significant bit (bit 7) is used, in A mode only, to disable the transfer of data at the input into the buffer register (cf. description of these two registers). The channel affected is then seen as being out of service. The other seven bits (bits 0 - 6) select the value of the time-delay used to detect the presence of a "gap". This is the space between two consecutive messages, the minimum duration of which is four periods of the transmit clock. This value is loaded into the register by the microprocessor, in A mode, at the same time as the enable bit. In B mode, this value is selected from two hardwired values, according to the state on pin IRQ/V. If n is the programmed value, the gap detection time-delay will be (8n - 4) 4 period of clock O.
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Input Register This 32-bit shift register receives the data corresponding to the messages. The message received is transferred into the registers on its output side if: * * * * * a gap detection signal has previously occurred, the registers which will receive the transferred data are not being read, the parity of the received message is correct if the circuit is programmed with the parity check enabled, the enable bit of the synchronization/enable register is set to 1 (A mode only), in A mode, the first eight bits received correspond to the programmed label (cf. description of label register).
Label Register
In A mode, this eight-bit register is programmed by the microprocessor. It contains the label to be recognized. In B mode, this register receives the first eight bits of the received message transferred from the input register. In this case, this register may be read by the external automatic scanning device.
Buffer Register
This 24-bit register receives data transferred from the input register. It may be read by the microprocessor in A mode or by the external automatic scanning device in B mode.
Circuit Operation
Logic Convention
"1" (high state) = most positive level "0" (low state) = most negative level
Operation of a Receive Channel
Data Acquisition Serial data is received on the "low" and the "high" lines (Hi and Li inputs). The Clock is reconstructed by OR-ing these inputs. Data is then directed towards a 32-bit shift register. Parity is computed. The reconstructed clock fall edge resets the message synchronization counter. This counter is incremented on each O: 8 clock period and delivers a word synchronization signal (gap) as described below (Figure 2) when reading a programmed value. Figure 2. Gap Detection
Clock max gap Counter 0 Synchro Predetermined value
The predetermined value together with an enable bit is loaded in the internal synchro/validation register when in A mode; it is chosen between two hardware programmed values when in B mode, according to the IRQ/V pin. 5
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Then: * When in A Mode The first 8 bits (M0-M7) that are received, are bits compared to a programmed word (label), this for each channel. If identical, the 24 other bits of the shift register are transferred in a 24-bit buffer register. The corresponding status bit is switched to 1 and the IRQ line is activated (IRQ = 0). If the channel enable bit is in the low state, transfer is not executed and the IRQ line is not activated. * When in B Mode All the shift register bits are transferred in the label and the 24-bit buffer register. Transfers are inhibited if the message parity is wrong in either mode (even number of bits in the high state) and if the circuit is programmed for parity check (Mode pin). This last one generates a O + n frequency square wave, n being the programmed value (the least significant bit being always set to 0). Then successively addresses the 8-bit bytes of the 24-bit buffer which are then available on the bus (D0-D7). Reading the last byte resets the corresponding status byte to the low state. The transfer from the receive register to the buffer register is inhibited from the "read" addressing of the channel (first or second byte) to the end of the last byte reading. * When in B Mode A divide by 4 counter is incremented on each O clock period and successively addresses the 4 channels. When the circuit is selected (CS = 0) and when A0 - A1 = 11, the label of the addressed channel is available on the bus (D0 - D7), as well as the channel number on the N0-N1 outputs. Counting is inhibited when RW/INH is in the high state. If the circuit is selected, the three bytes of the buffer register are then available on the bus when addressed through A0 A1 in the same way as A mode. The transfer from the receive register to the buffer register is done in the same way as A mode. In order to read the message corresponding to label received, CS has to stay activated to 0 during the reading of label and message RT1 - RT3 (minimum CS = 0 during the reading of the label and RT1). However CS has to stay activated to 0 during less than 30 clock periods of PHI (O).
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Operation of the Transmit Channel (only in A mode)
The transmit channel is composed of a 32-bit shift register and a programmable divider. The operation of this channel is controlled by the control register (C0 - C7). C4 selects the program of the transmit channel (see "Programming In A Mode (MODE = 0)" on page 7). The 4 bytes of the shift register are loaded (including the microprocessor computed parity bit). So is the divider by n register byte. The latter generates a divided by n frequency square wave, n being the programmed value (the least significant bit being always set to 0). Transmission starts when C5 is set to 1. The data of the shift register is then available on the 0 and 1 lines of the channel and is clocked out at the chosen frequency. The shift register is also feed forwarded so that data should not be lost. After the transmission of the 32nd bit, C5 is reset. The S4 bit is set to 1. It will be reset when C4 will be positioned to 1. The S7 bit of the status register is set to 1 during the transmission time. If C5 is set to 1 after transmission of the 32nd bit, the message is retransmitted after 4 transmit clock periods. The S4 status bit will also be reset when control bit C4 is set to 1. C6 is used for starting the receive channel testing. This test cannot be done during the reception of a message. If C6 = 1 the transmission channel signals are switched to the inputs of the control register selected receive channel. C6 is reset by any access to the control register. C7 is a mask bit of the S4 bit of the status register. If C7 = 0 and S4 = 1, the IRQ line will be activated. If C7 = 1, the IRQ line will not be activated by S4.
Note: C5 and C6 should be programmed at the same time in order to avoid transmission or test errors.
Programming In A Mode (MODE = 0)
When seen from the microprocessor, the circuit looks like 4 addresses ("read" or "write"). Addressing any register of a channel is done in two steps: * * channel addressing by the control register byte of the selected channel addressing
Thus, programming of the synchro registers or the labels and reading of the 24-bit buffers or the status register are possible. Loading of the transmit channel shift register is done through successive writing of the 4 bytes, the first being the label then RT1, RT2, RT3. The addresses of the 4 bytes are generated by an internal modulo-4 counter which is reset by any addressing of the control register (see Table 2 - Addressing with CS = 0 and Table 3 - Addressing of the channels by the control register).
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Table 2. Addressing with CS = 0
RW/INH A1 0 Read 1 0 1 1 0 Write 0 0 1 1 A0 0 1 0 1 0 1 0 1 Direct Addressing -- -- -- Status -- Control Not used -- Channel Addressing With the Control Register RT1 RT2 RT3 -- Synchro and divider by n -- -- Label
Table 3. Channel Addressing by the Control Register
C0 1 0 0 0 C1 x 1 0 0 C2 x x 1 0 C3 x x x 1 Channel Number channel 0 channel 1 channel 2 channel 3
The gap detection counters are incremented on each O divided by 8 clock period, if n is the synchro register value, the minimum detected gap length is (8n - 4) 4 O clock periods. C4 to C7 bits are independently interpreted. C4: Pile loading if A0 - A1 = 11 and divider by n if A0 - A1 = 00. The loading of the 4 bytes to be transmitted should be done immediately after positioning C4 to 1, this operation resetting the pile index at the level of the label byte. C5:Transmission start C6: Test mode C7: Transmit channel interrupt mask
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Figure 3. Bit Correspondence
Acquisition or transmission flow Acquisition register 31 Buffer register 7 RT3 07 RT2 0 7 RT1 0 7 7 7 7 LABEL 0 0 0 0
Bus D (0:7) Control C (0:7) Status S (0:7) Transmit shift Register Enable and synchro register Divider by n
4 RT3 RT2 RT1 LABEL
V6 7 1
0
Programming in B Mode (MODE = 1)
When in B mode, programming is done by hardware. The number of high speed channels is programmed on IRQ/V pin (see Table 4). The synchro register is set to 5 for high speed channels and to 32 for low speed channels. This corresponds to a nominal O clock frequency of 2 MHz and transmission frequencies of 12 to 14.5 kHz for low speed and of 99 to 101 kHz for high speed. Table 4. Programming of the IRQ/Vpin
IRQ/V 0: Low impedance 0: High impedance 1: Low impedance 1: High impedance High Speed Channel Numbers 0 0, 1 0, 1, 2
Parity Check
If the MODE pin senses a high impedance (typ. > 10 kW) the circuit checks the parity of the messages for each receive channel. If the number of received 1's in a message is even, the transfer is not done and the message is discarded (odd parity). When transmitting, the parity bit value is computed and loaded by the microprocessor or is the value of the received test message. If the MODE pin is directly strapped to VCC or VSS, parity check is not done.
Initialization
On power-on or when the RESET pin is set to 0, the following registers are reset to 0: * * * * control register status register the 4 label registers of the receive channels the 4 synchro registers.
The first gap after initialization is also ignored for each channel because acquired data could not be error-free.
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Electrical Characteristics
Maximum Ratings
Symbol VCC VIN TC Tstg Pd Rating Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Power Dissipation Tc = 125C Tc = 25C Tc = -55C Value -0.3 to +7 -0.3 to +7 TL to TH -55 to +125 -55 to +150 300 350 550 Unit Vdc Vdc C C mW mW mW
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields: however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Table 5. Thermal Characteristics (at 25C)
Package DIL 28 Symbol qJ-A qJ-C qJ-A qJ-C Parameter Thermal Resistance Junction-to-ambient Thermal Resistance Junction-to-case Thermal Resistance Junction-to-ambient Thermal Resistance Junction-to-case Value 50 10 45 9 Unit C/W C/W C/W C/W
LCCC 32
Power Considerations
The average chip-junction temperature, TJ, in C can be obtained from: TJ = TA + (PD x qJA) (1) TA = Ambient Temperature,C qJA = Package Thermal Resistance, Junction-to-Ambient,C/W PD = PINT + PI/O PINT = ICC x VCC,Watts - Chip Internal Power PI/O = Power Dissipation on Input and Output Pins - User Determined For most applications PI/O < PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K: (TJ + 273) Solving equations (1) and (2) for K gives: K = PD x (TA+ 273)+ qJA x PD2 (3) where K is a constant pertaining to the particular part K can be determined from equation (3) by measuring PD (at equilibrium) for a know TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. (2)
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The total thermal resistance of a package (qJA) can be separated into two components, qJC and qCA, representing the barrier to heat flow from the semiconductor junction to the package (case), surface (qJC) and from the case to the outside ambient (qCA). These terms are related by the equation:
qJA = qJC + qCA
(4)
qJC is device related and cannot be influenced by the user. However, qCA is user dependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling and thermal convection. Thus, good thermal management on the part of the user can significantly reduce qCA so that qJA approximately equals qJC. Substitution of q JC for q JA in equation (1) will result in a lower semiconductor junction temperature.
Table 6. Recommended Static Operating Conditions
Symbol VIH VIL VCC Parameter Input High Voltage Input Low Voltage Supply Voltage Min 2.0 -0.3 4.75 Max 5.25 0.8 5.25 Unit V V V
Table 7. Static Characteristics (VCC = 5.0V 5%; VSS = 0V; -55C < TC < + 125C)
Symbol VIH VIL Iin ITSI VOH Characteristics Input high voltage (except MODE, IRQ/V) Input low voltage (except MODE, IRQ/V) Input state leakage current (except MODE, IRQ/V) (VIN = 0.4 to 5.25V) Three state leakage current N0-N1, D0-D7 (VIN = 0.4 to 2.4V) Output high voltage (ILoad = -250 A) N0-N1, D0-D7 (ILoad = +10 A) IRQ/V Output high voltage (ILoad = 1.6 mA) N0-N1, D0-D7 (ILoad = 3.2 mA) IRQ/V Capacitance (Vin= 0, TC = 25C, f = 1 MHz) (except MODE, IRQ/V) External high programming impedance MODE, IRQ/V, (Cload 20pF) Scan frequency = f clock: 8) External low programming impedance Mode, IRQ/V (Cload 20 pF) Scan frequency = f clock: 8) 10 K Min 2.2 -0.3 -10 -10 10 Typ Max VCC 0.8 Unit V V A A
2.4 2.4
VCC VCC 0.4
V V
VOL
Cin
10
pF
RH
W
RL
10
W
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Table 7. Static Characteristics (Continued) (VCC = 5.0V 5%; VSS = 0V; -55C < TC < + 125C)
Symbol PD f F Characteristics Power dissipation Maximum operating frequency in A mode Maximum operating frequency in B mode 500 1000 Min Typ 310 Max 550 2000 2000 Unit mW kHz kHz
Dynamic Characteristics
.
Table 8. Bus Timing Characteristics (Load Conditions, see Figure 9) (VCC = 5.0V 5%; VSS = 0V; -55C < TC < +125C)
Symbol Characteristic Min Max Unit Read - A Mode (Figure 4) tAH TACC tDH Address Input Hold Time Data Access Time
(1)
A0-A1, RW/INH, CS D0-D7 D0-D7
10 300 10
ns ns ns
Data Output Hold Time
Write - A Mode (Figure 5) tAS A0-A1ns tAH tDS tDH Address Input Setup Time Address Input Hold Time Data Set Up Time Data Input Hold Time A0-A1, RW/INH, CS A0-A1, RW/INH, CS D0-D7 D0-D7 50 10 100 50 ns ns ns ns
Read - B Mode (Figure 6) tAS tAH tDH tACC Note: Address Setup Time Address Input Hold Time Data Output Hold Time Data Access Time A0-A1, RW/INH, CS A0-A1, RW/INH, CS 0-N1, D0-D7 N0-N1, D0-D7 50 10 10 300 ns ns ns ns
tSI RW/INH Setup Time 50 ns 1. See condition of validity for the access time of EF4442 status register at high temperature (Tc +85C) in "Annexe 1: EF4442 ARINC Controller/Bug Description:" on page 20.
Table 9. Clock Timing Characteristics (see Figure 8)
Symbol tCA tCB tWH tWL tr, tf Characteristic A Mode Cycle Time B Mode Cycle Time Pulse Width - Low 2000 Pulse Width - High Rise Time, Fall Time Min 500 500 180 180 Max 2000 1000 2000 2000 15 Unit ns ns ns ns ns
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Table 10. IRQ/V Output Timing Characteristics (see Figure 7)
Symbol tPHL tPHL Characteristic Delay Time - Low To High State Delay Time - High To Low State Max 1600 1000 Unit ns ns
Timing Diagrams
Figure 4. Read A Mode
0.5V tAH RW/INH CS A0-A1 2.3V 0.5V 2.3V 0.5V tACC D0-D7 2.3V 0.5V tDH
Figure 5. Write A Mode
0.5V tAS RW/INH CS A0-A1 0.5V 2.3V 0.5V tDS D0-D7 tDH tAH
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Figure 6. Read B Mode
0.5V tAS CS A0-A1 R/W/INH tACC D0-D7 N0-N1 2.3V 0.5V 2.3V 0.5V tSI 2.3V tDH 2.3V tAH
Figure 7. IRQ/V Output
2.3V tPLH IRQ/V 0.5V tPLH 2.3V
Figure 8. Clock
tCA or tCB 2.3V tr tWH
tf
Figure 9. Test Load
VCC RL = 2.2 k Test point 100 pF 56 k 1N 916 or Equiv. 1N 4148 or Equiv.
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Preparation For Delivery
Packaging
The microcircuits are packaged in a hermetically sealed package which is conformed to case outlines of MIL-STD-883 28 lead DIL/SB
Certificate of Compliance Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 or Atmel standard and guaranteeing the parameters are tested at extreme temperatures for the entire temperature range.
Handling
Devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: 1. Device should be handled on benches with conductive and grounded surface. 2. Ground test equipment, tools and operator. 3. Do not handle devices by the leads. 4. Store devices in conductive foam or carriers. 5. Avoid use of plastic, rubber, or silk. 6. Maintain relative humidity above 50%, if practical.
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Package Mechanical Data
DIL 28 - Ceramic Side Brazed Package
.080 .008 2.03 0.23 .010 .002 0.25 0.05 .600 Typ 15.24 Typ
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.050 .010 1.27 0.25
.233 Max 5.92 Max
.100 .005 2.54 0.13
.018 .002 0.46 0.05
28 .594 .008 15.09 0.20
15
1
Pin N 1 index 1.400 0.14 35.56 0.35
14
16
EF4442
.150 Min 3.81 Min
EF4442
DIP 28 - Plastic Dual In Line Package
4.45 0.63 14.10 max
0.23 to 0.31 3.30 1.27 0.45 33.02 15.20 to 16.68
37.34 max 28 15
1
14
DIL 28 - Cerdip Package (Obsolete Package, for Traceability Purpose Only)
.037 .022 0.94 0.56 .150 Min 3.81 Min
.100 Typ 2.54 Typ 28 .520 .006 13.21 0.15
.018 .001 0.46 0.05 15 .700 0.15 17.78 0.38
1 .00 .010 25 0.0 0.25
1
14 1.450 0.10 36.83 0.25
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LCCC32 - Leadless Ceramic Chip Carrier package (Obsolete Package, for Traceability Purpose Only) To Be Confirmed
TOP VIEW .072 .005 1.83 0.13 BOTTOM VIEW
+.010 .550 -.006 +0.25 13.97 -0.15
+.010 -.006 +0.25 11.43 -0.15 .450 .055 .005 1.40 0.13 .025 Typ 0.64 Typ
Terminal Designation
Figure 10. DIL 28/DIP 28
VSS R/W/INH N0 N1 CS A0 A1 RESET D7 D6 D5 D4 VCC
.050 Typ 1.27 Typ
1 2 3 4 5 6 TOP 7 VIEW 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
MODE IRQ/V H3 L3 H2 L2 H1 L1 H0 L0 D0 D1 D2 D3
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Figure 11. LCCC 32 (Obsolete Package)
20 21 NC L0 H0 L1 H1 L2 H2 L3 H3 29 30 D0 D1 D2 D3 VCC D4 NC TOP VIEW NC IRQ/V MODE VSS 14 13 D5 D6 D7 RESET A1 A0 CS NC 5 R/W/INH N0 N1 4
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Ordering Information
Table 11. Hi-REL Product
Commercial Atmel Part-Number EF4442CMG/BZ63 EF4442CMB/TZ63 EF4442PVZ63 Norms NFC 96883 According to MIL-STD-883 Atmel Standard Package DIL 28 Side Brazed DIL 28 Side Brazed DIP 28 Temperature Range Tc (C) -55/ +125 -55/ +125 -40/ +85 Class G B Drawing Number Data sheet Data sheet Data sheet
Annexe 1: EF4442 ARINC Controller/Bug Description:
Condition of Validity for the Access Time in A mode (Tacc) of EF4442 Status Register at High Temperature (TCASE 85C).
Description Conditions
In a particular condition described here after, the access time (Tacc) of EF4442 status register is above the maximum value specified in Table 8. The defect appears for high temperature 85C and +125C. When the RTA starts a new transmission in A mode, the S7 bit of the status register is set to 1 after 4 transmit clock periods. If this S7 bit is read before it has risen to 1 (i.e. S7 = 0), then the first access time (Tacc) for S7 = 1 will be longer than the specification: * * maximum value up to 400 ns for military range part number (M), maximum value up to 330 ns for industrial range part number (V).
If a second read is performed to the S7 bit, the access time (Tacc) will be compliant with the specification (max value = 300 ns).
Workaround 1
After a new transmission start in A mode (bit C5 of control register = 1), the status register does not have to be read before the S7 bit is set to 1. In that case the access time would be correct. Perform two successive read access to the Status register. The second access time would be correct.
Workaround 2
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ASIC/ASSP/Smart Cards
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
2112A-HIREL-11/02 0M

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